PCB-Challenge-2026 - my entry for PCB Challenge

	Commit message (Collapse)	Author	Age	Files	Lines
*	finish a part of the input interface	hmjsp	9 days	1	-2184/+2698
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*	add all repeated layouts	hmjsp	9 days	1	-2735/+7057
\| \| \| \| \|	- all that is left is to wire up non repetitive sections and connect everything
*	make layout and repeat for notand	hmjsp	9 days	1	-822/+990
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*	fix compatibility with rules	hmjsp	9 days	1	-217/+384
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*	modified multflop to be compatible with rules	hmjsp	9 days	1	-539/+611
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*	temporary commit; realised i can't route under ICs so preserving state ↵	hmjsp	10 days	1	-2331/+2510
\| \| \| \|	before redoing
*	fix some DRC errors	hmjsp	10 days	1	-1323/+1404
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*	connected some repetitive components together; commit for safety	hmjsp	10 days	1	-45151/+50594
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*	Add files via upload	Paul Vincent Bezzina	13 days	1	-309/+340
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*	Removed the mysterious U2	Paul Vincent Bezzina	13 days	1	-589/+1
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*	Fixed reported schematic and PCB issues	Paul Vincent Bezzina	13 days	1	-2717/+4861
\| \| \|	C1-C8, R1 and SW1 and SW3 were not assigned a footprint. Few mistakes with the net labels now resolved Transistors actually have nets.
*	Resolved issue with 3V3 and +3.3V differences on the schematic	Paul Vincent Bezzina	14 days	1	-1/+41
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*	Add files via upload	Paul Vincent Bezzina	2026-10-07	1	-0/+43524
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*	Delete main/pcb_challenge_final.kicad_pcb	Paul Vincent Bezzina	2026-10-07	1	-43509/+0
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*	Add files via upload	Paul Vincent Bezzina	2026-09-15	1	-0/+43509
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*	Delete main/pcb_challenge_final.kicad_pcb	Paul Vincent Bezzina	2026-09-15	1	-43635/+0
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*	Add files via upload	Paul Vincent Bezzina	2026-09-15	1	-0/+43635