From d9f4338c860e41a2ee1850d20083748006625e7b Mon Sep 17 00:00:00 2001 From: hmjsp Date: Sun, 18 Oct 2026 11:19:36 +0100 Subject: fix compatibility with rules --- main/pcb_challenge_final.kicad_pcb | 601 ++++++++++++++++++++++++------------- 1 file changed, 384 insertions(+), 217 deletions(-) diff --git a/main/pcb_challenge_final.kicad_pcb b/main/pcb_challenge_final.kicad_pcb index 56fc4c0..cada320 100644 --- a/main/pcb_challenge_final.kicad_pcb +++ b/main/pcb_challenge_final.kicad_pcb @@ -9972,13 +9972,13 @@ (footprint "Package_TO_SOT_SMD:SOT-553" (layer "F.Cu") (uuid "37edfd10-044a-42cd-b05a-b4c692c06010") - (at 49.735 134.731814 -90) + (at 50.9025 135.85 -90) (descr "SOT, 5 Pin (https://www.jedec.org/system/files/docs/MO-293B.pdf)") (tags "SOT TO_SOT_SMD JEDEC-MO-293-UAAD-1 Texas-DRL-5") (property "Reference" "U58" (at 0 -1.65 90) (layer "F.SilkS") - (uuid "17cde2df-15d4-4d45-9c4a-fd7a798db8b0") + (uuid "1907c6f8-c657-4fee-8c3f-4263e152466e") (effects (font (size 1 1) @@ -9989,7 +9989,7 @@ (property "Value" "74LVC1GU04DRL" (at 0 1.65 90) (layer "F.Fab") - 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