From 54216dd720ea6d1092c72dda5cfdecc4790be3cc Mon Sep 17 00:00:00 2001
From: Paul Vincent Bezzina <109743463+Vertrex-star@users.noreply.github.com>
Date: Wed, 14 Oct 2026 08:03:59 +0100
Subject: Update README.md

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 README.md | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

(limited to 'README.md')

diff --git a/README.md b/README.md
index 69b3197..142acb4 100644
--- a/README.md
+++ b/README.md
@@ -73,9 +73,8 @@ The keep out zone of the ESP32 antenna does not have to cover any PCB area, it c
 - Boards do not need to retain fully legible silkscreen labelling. 
 
 ### DRC Pass Criteria
-- All submitted boards must pass KiCad's Design Rule Checker (Inspect → Design Rules Checker) with **zero unresolved DRC errors**.
+- All submitted boards must pass KiCad's Design Rule Checker (Inspect → Design Rules Checker) to a good degree. I understand that the DRC can be quite buggy especially with imported footprints, thus I will be a bit lenient. 
 - DRC **warnings** (e.g. minor silkscreen clipping) will not disqualify a board, but excessive or careless warnings may count against a board at the routing quality tie break stage.
-- A board with unresolved DRC errors is disqualified from the size based ranking regardless of its footprint area.
 
 ### Note on High-Speed & Power Rules
 The challenge schematic does include a high speed signal paths (a differential pair requiring a continuous reference plane). It does not however have a significant power delivery requirement (e.g. wide power traces, stitching vias). As such, no specific power plane rules are imposed in this iteration. 
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