From 3786e0f756fbfde4ea1e56f8087292df550b29f5 Mon Sep 17 00:00:00 2001
From: Paul Vincent Bezzina <109743463+Vertrex-star@users.noreply.github.com>
Date: Wed, 14 Oct 2026 12:53:39 +0100
Subject: Issues resolved

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+## Issues
+1. C1-C8, R1, SW1 and SW3 did not have a footprint. 
+2. The transistor did not have the correct nets due to being numbered 1, 5 and 6 rather than 1, 2 and 3. 
+3. 3v3 instead of +3.3V power net. 
+4. Input 1,  Input2, Input 3 and Input 4 rather than b1, b2, b3 and 4.
+
+#### Credits to: 
+Mickey Techachokwiwat and Lutfi Cengiz for finding these issues and reporting them to me.
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