From 3790d3b588130668b2d9832a9fe209a65a471ea7 Mon Sep 17 00:00:00 2001
From: Paul Vincent Bezzina <109743463+Vertrex-star@users.noreply.github.com>
Date: Wed, 14 Oct 2026 12:31:13 +0100
Subject: Fixed reported schematic and PCB issues

C1-C8, R1 and SW1 and SW3 were not assigned a footprint. Few mistakes with the net labels now resolved Transistors actually have nets.
---
 main/~pcb_challenge_final.kicad_pcb.lck | 1 +
 1 file changed, 1 insertion(+)
 create mode 100644 main/~pcb_challenge_final.kicad_pcb.lck

(limited to 'main/~pcb_challenge_final.kicad_pcb.lck')

diff --git a/main/~pcb_challenge_final.kicad_pcb.lck b/main/~pcb_challenge_final.kicad_pcb.lck
new file mode 100644
index 0000000..5059ec7
--- /dev/null
+++ b/main/~pcb_challenge_final.kicad_pcb.lck
@@ -0,0 +1 @@
+{"hostname":"PAUL","username":"paulv"}
\ No newline at end of file
-- 
cgit v1.2.3