From cfaee50808ef292fb3a283722a44f8d58ab12638 Mon Sep 17 00:00:00 2001
From: Paul Vincent Bezzina <109743463+Vertrex-star@users.noreply.github.com>
Date: Wed, 14 Oct 2026 12:38:44 +0100
Subject: Resolved issues

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 main/issues_resolved.md | 3 +++
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 create mode 100644 main/issues_resolved.md

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+C1-C8, R1, SW1 and SW3 did not have a footprint. The transistor did not have the correct nets due to being numbered 1, 5 and 6 rather than 1, 2 and 3. 
+3v3 instead of +3.3V power net. 
+Input 1,  Input2, Input 3 and Input 4 rather than b1, b2, b3 and 4.
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