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| author | Paul Vincent Bezzina <109743463+Vertrex-star@users.noreply.github.com> | 2026-09-15 02:14:56 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2026-09-15 02:14:56 +0100 |
| commit | 1096c9206824952d159097abf91a549e81d76f5e (patch) | |
| tree | 1bd9a04a87ca92fa2a4e55add1ae753904bb8d21 | |
| parent | 334b2a9b3d5dfa68f678c9cba7078be73a2914bb (diff) | |
| download | PCB-Challenge-2026-1096c9206824952d159097abf91a549e81d76f5e.zip | |
Update README.md
| -rw-r--r-- | README.md | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -50,7 +50,7 @@ From my own experience, no matter how much you may like designing PCBs, ultimate - A board with unresolved DRC errors is disqualified from the size based ranking regardless of its footprint area. ### Note on High-Speed & Power Rules -The challenge schematic does not include high speed signal paths (e.g. differential pairs requiring a continuous reference/return plane) or significant power delivery requirements (e.g. wide power traces, stitching vias). As such, no specific high speed routing or power plane rules are imposed in this iteration. Should a future version of the challenge include such elements, this rule set will be updated accordingly. +The challenge schematic does include a high speed signal paths (a differential pair requiring a continuous reference plane). It does not however have a significant power delivery requirement (e.g. wide power traces, stitching vias). As such, no specific power plane rules are imposed in this iteration. ## Judging Criteria |
