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authorPaul Vincent Bezzina <109743463+Vertrex-star@users.noreply.github.com>2026-10-13 12:07:59 +0100
committerGitHub <noreply@github.com>2026-10-13 12:07:59 +0100
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## Project Description
-This board is a **serial input 8 bit adder with a fixed value match detector**. Two single bit data streams (Input 1 and Input 2) are clocked into two separate 8-bit serial in/parallel out shift registers. Once eight bits have been loaded, the two bytes are added by a cascaded 8 bit binary adder. The sum goes to a hard-wired equality comparator, which raises the output **F** only when the sum equals a predetermined constant.
+This board is a **serial input 8 bit adder with a fixed value match detector**. Two single bit data streams (Input 1 and Input 2) are clocked into two separate 8 bit serial in/parallel out shift registers. Once eight bits have been loaded, the two bytes are added by a cascaded 8 bit binary adder. The sum goes to a hard-wired equality comparator, which raises the output **F** only when the sum equals a predetermined constant.
## Functional Blocks