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| author | Paul Vincent Bezzina <109743463+Vertrex-star@users.noreply.github.com> | 2026-10-14 08:21:45 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2026-10-14 08:21:45 +0100 |
| commit | 7f67d3cc489d78c30c57581d2506a239b845f62c (patch) | |
| tree | 2b794ad54662c37bd467e8315ad7ac4588e3cae9 /README.md | |
| parent | 4fcd35be455b108e31c650c029a0a56aa315fd24 (diff) | |
| download | PCB-Challenge-2026-7f67d3cc489d78c30c57581d2506a239b845f62c.zip | |
Update README.md
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -73,7 +73,7 @@ The keep out zone of the ESP32 antenna does not have to cover any PCB area, it c - Boards do not need to retain fully legible silkscreen labelling. ### DRC Pass Criteria -- All submitted boards must pass KiCad's Design Rule Checker to a good degree (Inspect → Design Rules Checker) to a good degree. I understand that the DRC can be quite buggy especially with imported footprints, thus I will be a bit lenient. +- All submitted boards must pass KiCad's Design Rule Checker to a good degree (Inspect → Design Rules Checker). I understand that the DRC can be quite buggy especially with imported footprints, thus I will be a bit lenient. - DRC **warnings** (e.g. minor silkscreen clipping) will not disqualify a board, but excessive or careless warnings may count against a board at the routing quality tie break stage. #### I am aware that there is an issue with the flip flop footprints and we will ignore any DRC errors associated with them. Just ensure you use a trace width of 0.17 for them. |
