summaryrefslogtreecommitdiff
path: root/main/pcb_challenge_final.kicad_pcb
diff options
context:
space:
mode:
Diffstat (limited to 'main/pcb_challenge_final.kicad_pcb')
-rw-r--r--main/pcb_challenge_final.kicad_pcb42
1 files changed, 41 insertions, 1 deletions
diff --git a/main/pcb_challenge_final.kicad_pcb b/main/pcb_challenge_final.kicad_pcb
index 50be5ba..bac3080 100644
--- a/main/pcb_challenge_final.kicad_pcb
+++ b/main/pcb_challenge_final.kicad_pcb
@@ -34,6 +34,45 @@
(45 "User.4" user)
)
(setup
+ (stackup
+ (layer "F.SilkS"
+ (type "Top Silk Screen")
+ )
+ (layer "F.Paste"
+ (type "Top Solder Paste")
+ )
+ (layer "F.Mask"
+ (type "Top Solder Mask")
+ (thickness 0.01)
+ )
+ (layer "F.Cu"
+ (type "copper")
+ (thickness 0.035)
+ )
+ (layer "dielectric 1"
+ (type "core")
+ (thickness 1.51)
+ (material "FR4")
+ (epsilon_r 4.5)
+ (loss_tangent 0.02)
+ )
+ (layer "B.Cu"
+ (type "copper")
+ (thickness 0.035)
+ )
+ (layer "B.Mask"
+ (type "Bottom Solder Mask")
+ (thickness 0.01)
+ )
+ (layer "B.Paste"
+ (type "Bottom Solder Paste")
+ )
+ (layer "B.SilkS"
+ (type "Bottom Silk Screen")
+ )
+ (copper_finish "None")
+ (dielectric_constraints no)
+ )
(pad_to_mask_clearance 0)
(allow_soldermask_bridges_in_footprints no)
(tenting
@@ -50,6 +89,7 @@
)
(capping no)
(filling no)
+ (zone_defaults)
(pcbplotparams
(layerselection 0x00000000_00000000_55555555_5755f5ff)
(plot_on_all_layers_selection 0x00000000_00000000_00000000_00000000)
@@ -26092,7 +26132,7 @@
(at -7 -1.7)
(size 0.8 0.4)
(layers "F.Cu" "F.Mask" "F.Paste")
- (net "3v3")
+ (net "+3.3V")
(pinfunction "3V3_3")
(pintype "power_in")
(uuid "d61db001-f020-448e-b0b4-0ff5899a42cc")