summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAgeFilesLines
* Issues resolvedPaul Vincent Bezzina13 days1-0/+0
|
* Issues resolvedPaul Vincent Bezzina13 days1-3/+8
|
* Resolved issuesPaul Vincent Bezzina13 days1-0/+3
|
* Delete main/~pcb_challenge_final.kicad_pcb.lckPaul Vincent Bezzina13 days1-1/+0
|
* Delete main/~pcb_challenge_final.kicad_pro.lckPaul Vincent Bezzina13 days1-1/+0
|
* Fixed reported schematic and PCB issuesPaul Vincent Bezzina13 days4-4352/+6514
| | | C1-C8, R1 and SW1 and SW3 were not assigned a footprint. Few mistakes with the net labels now resolved Transistors actually have nets.
* Updated rules regarding DRCPaul Vincent Bezzina14 days1-1/+1
|
* Update README.mdPaul Vincent Bezzina14 days1-1/+1
|
* Resolved issue with 3V3 and +3.3V differences on the schematicPaul Vincent Bezzina14 days4-95/+144
|
* Update README.mdPaul Vincent Bezzina14 days1-1/+1
|
* Update README.mdPaul Vincent Bezzina14 days1-3/+3
|
* Update README.mdPaul Vincent Bezzina14 days1-1/+1
|
* Update README.mdPaul Vincent Bezzina14 days1-0/+2
|
* Update README.mdPaul Vincent Bezzina14 days1-2/+1
|
* Update README.mdPaul Vincent Bezzina14 days1-1/+1
|
* Update answer.mdPaul Vincent Bezzina2026-10-131-1/+1
|
* Create answer.mdPaul Vincent Bezzina2026-10-131-0/+45
|
* Update README.mdPaul Vincent Bezzina2026-10-121-1/+1
|
* Update README.mdPaul Vincent Bezzina2026-10-091-2/+2
|
* Update README.mdPaul Vincent Bezzina2026-10-091-1/+1
|
* Update README.mdPaul Vincent Bezzina2026-10-091-1/+1
|
* Update README.mdPaul Vincent Bezzina2026-10-091-1/+1
|
* Add files via uploadPaul Vincent Bezzina2026-10-091-0/+0
|
* Delete assets/sponsors/janestreet.pngPaul Vincent Bezzina2026-10-091-0/+0
|
* Add files via uploadPaul Vincent Bezzina2026-10-091-0/+0
|
* Add files via uploadPaul Vincent Bezzina2026-10-091-0/+0
|
* Delete assets/sponsors/janestreet.pngPaul Vincent Bezzina2026-10-091-0/+0
|
* Add files via uploadPaul Vincent Bezzina2026-10-091-0/+0
|
* Update README.mdPaul Vincent Bezzina2026-10-091-1/+1
|
* Rename pcbway to pcbway.pngPaul Vincent Bezzina2026-10-091-0/+0
|
* Add files via uploadPaul Vincent Bezzina2026-10-092-0/+0
|
* Update README.mdPaul Vincent Bezzina2026-10-091-0/+30
|
* Add files via uploadPaul Vincent Bezzina2026-10-081-0/+0
|
* Add files via uploadPaul Vincent Bezzina2026-10-083-425/+8033
|
* Update README.mdPaul Vincent Bezzina2026-10-070-0/+0
|
* Add files via uploadPaul Vincent Bezzina2026-10-073-1/+96108
|
* Delete main/pcb_challenge_final.kicad_pcbPaul Vincent Bezzina2026-10-071-43509/+0
|
* Delete main/pcb_challenge_final.kicad_schPaul Vincent Bezzina2026-10-071-49312/+0
|
* Add files via uploadPaul Vincent Bezzina2026-10-071-0/+0
|
* Delete schematic.pngPaul Vincent Bezzina2026-10-071-0/+0
|
* Update README.mdPaul Vincent Bezzina2026-10-071-2/+5
|
* Update README.mdPaul Vincent Bezzina2026-09-241-1/+1
|
* Update README.mdPaul Vincent Bezzina2026-09-241-2/+2
|
* Add files via uploadPaul Vincent Bezzina2026-09-211-0/+49312
|
* Delete main/pcb_challenge_final.kicad_schPaul Vincent Bezzina2026-09-211-48411/+0
|
* Add files via uploadPaul Vincent Bezzina2026-09-211-0/+0
|
* Update README.mdPaul Vincent Bezzina2026-09-211-1/+3
|
* Update README.mdPaul Vincent Bezzina2026-09-161-0/+2
|
* Update README.mdPaul Vincent Bezzina2026-09-161-1/+1
|
* Update README.mdPaul Vincent Bezzina2026-09-151-0/+2
|
Entia non sunt multiplicanda praeter necessitatem.