| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | connect some components across pcb | hmjsp | 8 days | 1 | -262/+3384 |
| * | connect 4 pin inputs | hmjsp | 8 days | 1 | -398/+1414 |
| * | add IOs to other side | hmjsp | 8 days | 2 | -323/+1195 |
| * | board kind of taking shape, need to connect IOs | hmjsp | 8 days | 2 | -7378/+8380 |
| * | add previously missing footprints and connect them | hmjsp | 8 days | 2 | -3123/+6889 |
| * | temporary commit | hmjsp | 8 days | 1 | -8841/+7820 |
| * | temporary commit | hmjsp | 8 days | 2 | -6601/+5267 |
| * | temporary commit | hmjsp | 9 days | 1 | -1014/+1341 |
| * | add most components to memory | hmjsp | 9 days | 1 | -1000/+1963 |
| * | checkpoint; i forgot what i even changed | hmjsp | 9 days | 2 | -362/+724 |
| * | checkpoint; made out4 stuck and preserving before fixing | hmjsp | 9 days | 1 | -784/+1668 |
| * | checkpoint; fully connect a bunch of components | hmjsp | 9 days | 2 | -3400/+5275 |
| * | connect usb-c components; start grouping and putting stuff together | hmjsp | 9 days | 2 | -1486/+2938 |
| * | finish a part of the input interface | hmjsp | 9 days | 2 | -2185/+2699 |
| * | add all repeated layouts | hmjsp | 9 days | 1 | -2735/+7057 |
| * | make layout and repeat for notand | hmjsp | 9 days | 1 | -822/+990 |
| * | fix compatibility with rules | hmjsp | 9 days | 1 | -217/+384 |
| * | modified multflop to be compatible with rules | hmjsp | 9 days | 2 | -543/+611 |
| * | temporary commit; realised i can't route under ICs so preserving state before... | hmjsp | 10 days | 1 | -2331/+2510 |
| * | fix some DRC errors | hmjsp | 10 days | 2 | -1327/+1408 |
| * | connected some repetitive components together; commit for safety | hmjsp | 10 days | 4 | -105226/+111154 |
| * | Update README.md | Paul Vincent Bezzina | 11 days | 1 | -1/+1 |
| * | Add files via upload | Paul Vincent Bezzina | 13 days | 1 | -309/+340 |
| * | Issues | Paul Vincent Bezzina | 13 days | 1 | -1/+1 |
| * | Update README.md | Paul Vincent Bezzina | 13 days | 1 | -1/+1 |
| * | Issues | Paul Vincent Bezzina | 13 days | 1 | -1/+1 |
| * | Issues | Paul Vincent Bezzina | 13 days | 1 | -1/+1 |
| * | Update readme.md | Paul Vincent Bezzina | 13 days | 1 | -0/+2 |
| * | Removed the mysterious U2 | Paul Vincent Bezzina | 13 days | 1 | -589/+1 |
| * | Issues resolved | Paul Vincent Bezzina | 13 days | 1 | -0/+0 |
| * | Issues resolved | Paul Vincent Bezzina | 13 days | 1 | -3/+8 |
| * | Resolved issues | Paul Vincent Bezzina | 13 days | 1 | -0/+3 |
| * | Delete main/~pcb_challenge_final.kicad_pcb.lck | Paul Vincent Bezzina | 13 days | 1 | -1/+0 |
| * | Delete main/~pcb_challenge_final.kicad_pro.lck | Paul Vincent Bezzina | 13 days | 1 | -1/+0 |
| * | Fixed reported schematic and PCB issues | Paul Vincent Bezzina | 13 days | 4 | -4352/+6514 |
| * | Updated rules regarding DRC | Paul Vincent Bezzina | 13 days | 1 | -1/+1 |
| * | Update README.md | Paul Vincent Bezzina | 13 days | 1 | -1/+1 |
| * | Resolved issue with 3V3 and +3.3V differences on the schematic | Paul Vincent Bezzina | 14 days | 4 | -95/+144 |
| * | Update README.md | Paul Vincent Bezzina | 14 days | 1 | -1/+1 |
| * | Update README.md | Paul Vincent Bezzina | 14 days | 1 | -3/+3 |
| * | Update README.md | Paul Vincent Bezzina | 14 days | 1 | -1/+1 |
| * | Update README.md | Paul Vincent Bezzina | 14 days | 1 | -0/+2 |
| * | Update README.md | Paul Vincent Bezzina | 14 days | 1 | -2/+1 |
| * | Update README.md | Paul Vincent Bezzina | 14 days | 1 | -1/+1 |
| * | Update answer.md | Paul Vincent Bezzina | 2026-10-13 | 1 | -1/+1 |
| * | Create answer.md | Paul Vincent Bezzina | 2026-10-13 | 1 | -0/+45 |
| * | Update README.md | Paul Vincent Bezzina | 2026-10-12 | 1 | -1/+1 |
| * | Update README.md | Paul Vincent Bezzina | 2026-10-09 | 1 | -2/+2 |
| * | Update README.md | Paul Vincent Bezzina | 2026-10-09 | 1 | -1/+1 |
| * | Update README.md | Paul Vincent Bezzina | 2026-10-09 | 1 | -1/+1 |
 |
index : PCB-Challenge-2026 | |
| my entry for PCB Challenge |
| summaryrefslogtreecommitdiff |