PCB-Challenge-2026 - my entry for PCB Challenge

	Commit message (Collapse)	Author	Age	Files	Lines
*	temporary commit	hmjsp	9 days	1	-1014/+1341
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*	add most components to memory	hmjsp	9 days	1	-1000/+1963
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*	checkpoint; i forgot what i even changed	hmjsp	9 days	2	-362/+724
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*	checkpoint; made out4 stuck and preserving before fixing	hmjsp	9 days	1	-784/+1668
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*	checkpoint; fully connect a bunch of components	hmjsp	9 days	2	-3400/+5275
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*	connect usb-c components; start grouping and putting stuff together	hmjsp	9 days	2	-1486/+2938
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*	finish a part of the input interface	hmjsp	9 days	2	-2185/+2699
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*	add all repeated layouts	hmjsp	9 days	1	-2735/+7057
\| \| \| \| \|	- all that is left is to wire up non repetitive sections and connect everything
*	make layout and repeat for notand	hmjsp	9 days	1	-822/+990
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*	fix compatibility with rules	hmjsp	9 days	1	-217/+384
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*	modified multflop to be compatible with rules	hmjsp	10 days	2	-543/+611
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*	temporary commit; realised i can't route under ICs so preserving state ↵	hmjsp	10 days	1	-2331/+2510
\| \| \| \|	before redoing
*	fix some DRC errors	hmjsp	10 days	2	-1327/+1408
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*	connected some repetitive components together; commit for safety	hmjsp	10 days	4	-105226/+111154
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*	Update README.md	Paul Vincent Bezzina	11 days	1	-1/+1
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*	Add files via upload	Paul Vincent Bezzina	13 days	1	-309/+340
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*	Issues	Paul Vincent Bezzina	13 days	1	-1/+1
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*	Update README.md	Paul Vincent Bezzina	13 days	1	-1/+1
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*	Issues	Paul Vincent Bezzina	13 days	1	-1/+1
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*	Issues	Paul Vincent Bezzina	13 days	1	-1/+1
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*	Update readme.md	Paul Vincent Bezzina	13 days	1	-0/+2
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*	Removed the mysterious U2	Paul Vincent Bezzina	13 days	1	-589/+1
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*	Issues resolved	Paul Vincent Bezzina	13 days	1	-0/+0
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*	Issues resolved	Paul Vincent Bezzina	13 days	1	-3/+8
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*	Resolved issues	Paul Vincent Bezzina	13 days	1	-0/+3
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*	Delete main/~pcb_challenge_final.kicad_pcb.lck	Paul Vincent Bezzina	13 days	1	-1/+0
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*	Delete main/~pcb_challenge_final.kicad_pro.lck	Paul Vincent Bezzina	13 days	1	-1/+0
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*	Fixed reported schematic and PCB issues	Paul Vincent Bezzina	13 days	4	-4352/+6514
\| \| \|	C1-C8, R1 and SW1 and SW3 were not assigned a footprint. Few mistakes with the net labels now resolved Transistors actually have nets.
*	Updated rules regarding DRC	Paul Vincent Bezzina	14 days	1	-1/+1
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*	Update README.md	Paul Vincent Bezzina	14 days	1	-1/+1
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*	Resolved issue with 3V3 and +3.3V differences on the schematic	Paul Vincent Bezzina	14 days	4	-95/+144
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*	Update README.md	Paul Vincent Bezzina	14 days	1	-1/+1
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*	Update README.md	Paul Vincent Bezzina	14 days	1	-3/+3
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*	Update README.md	Paul Vincent Bezzina	14 days	1	-1/+1
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*	Update README.md	Paul Vincent Bezzina	14 days	1	-0/+2
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*	Update README.md	Paul Vincent Bezzina	14 days	1	-2/+1
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*	Update README.md	Paul Vincent Bezzina	14 days	1	-1/+1
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*	Update answer.md	Paul Vincent Bezzina	2026-10-13	1	-1/+1
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*	Create answer.md	Paul Vincent Bezzina	2026-10-13	1	-0/+45
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*	Update README.md	Paul Vincent Bezzina	2026-10-12	1	-1/+1
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*	Update README.md	Paul Vincent Bezzina	2026-10-09	1	-2/+2
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*	Update README.md	Paul Vincent Bezzina	2026-10-09	1	-1/+1
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*	Update README.md	Paul Vincent Bezzina	2026-10-09	1	-1/+1
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*	Update README.md	Paul Vincent Bezzina	2026-10-09	1	-1/+1
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*	Add files via upload	Paul Vincent Bezzina	2026-10-09	1	-0/+0
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*	Delete assets/sponsors/janestreet.png	Paul Vincent Bezzina	2026-10-09	1	-0/+0
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*	Add files via upload	Paul Vincent Bezzina	2026-10-09	1	-0/+0
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*	Add files via upload	Paul Vincent Bezzina	2026-10-09	1	-0/+0
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*	Delete assets/sponsors/janestreet.png	Paul Vincent Bezzina	2026-10-09	1	-0/+0
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*	Add files via upload	Paul Vincent Bezzina	2026-10-09	1	-0/+0
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