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* add previously missing footprints and connect themhmjsp8 days2-3123/+6889
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* temporary commithmjsp8 days1-8841/+7820
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* temporary commithmjsp8 days2-6601/+5267
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* temporary commithmjsp9 days1-1014/+1341
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* add most components to memoryhmjsp9 days1-1000/+1963
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* checkpoint; i forgot what i even changedhmjsp9 days2-362/+724
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* checkpoint; made out4 stuck and preserving before fixinghmjsp9 days1-784/+1668
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* checkpoint; fully connect a bunch of componentshmjsp9 days2-3400/+5275
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* connect usb-c components; start grouping and putting stuff togetherhmjsp9 days2-1486/+2938
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* finish a part of the input interfacehmjsp9 days2-2185/+2699
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* add all repeated layoutshmjsp9 days1-2735/+7057
| | | | | - all that is left is to wire up non repetitive sections and connect everything
* make layout and repeat for notandhmjsp9 days1-822/+990
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* fix compatibility with ruleshmjsp9 days1-217/+384
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* modified multflop to be compatible with ruleshmjsp9 days2-543/+611
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* temporary commit; realised i can't route under ICs so preserving state ↵hmjsp10 days1-2331/+2510
| | | | before redoing
* fix some DRC errorshmjsp10 days2-1327/+1408
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* connected some repetitive components together; commit for safetyhmjsp10 days4-105226/+111154
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* Add files via uploadPaul Vincent Bezzina13 days1-309/+340
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* IssuesPaul Vincent Bezzina13 days1-1/+1
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* IssuesPaul Vincent Bezzina13 days1-1/+1
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* IssuesPaul Vincent Bezzina13 days1-1/+1
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* Update readme.mdPaul Vincent Bezzina13 days1-0/+2
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* Removed the mysterious U2Paul Vincent Bezzina13 days1-589/+1
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* Issues resolvedPaul Vincent Bezzina13 days1-0/+0
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* Issues resolvedPaul Vincent Bezzina13 days1-3/+8
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* Resolved issuesPaul Vincent Bezzina13 days1-0/+3
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* Delete main/~pcb_challenge_final.kicad_pcb.lckPaul Vincent Bezzina13 days1-1/+0
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* Delete main/~pcb_challenge_final.kicad_pro.lckPaul Vincent Bezzina13 days1-1/+0
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* Fixed reported schematic and PCB issuesPaul Vincent Bezzina13 days4-4352/+6514
| | | C1-C8, R1 and SW1 and SW3 were not assigned a footprint. Few mistakes with the net labels now resolved Transistors actually have nets.
* Resolved issue with 3V3 and +3.3V differences on the schematicPaul Vincent Bezzina14 days4-95/+144
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* Add files via uploadPaul Vincent Bezzina2026-10-083-425/+8033
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* Add files via uploadPaul Vincent Bezzina2026-10-073-1/+96108
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* Delete main/pcb_challenge_final.kicad_pcbPaul Vincent Bezzina2026-10-071-43509/+0
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* Delete main/pcb_challenge_final.kicad_schPaul Vincent Bezzina2026-10-071-49312/+0
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* Add files via uploadPaul Vincent Bezzina2026-09-211-0/+49312
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* Delete main/pcb_challenge_final.kicad_schPaul Vincent Bezzina2026-09-211-48411/+0
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* Delete main/deletePaul Vincent Bezzina2026-09-151-651/+0
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* Add files via uploadPaul Vincent Bezzina2026-09-153-0/+92571
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* Rename pcb_challenge_final.kicad_pro to deletePaul Vincent Bezzina2026-09-151-0/+0
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* Delete main/pcb_challenge_final.kicad_schPaul Vincent Bezzina2026-09-151-48411/+0
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* Delete main/pcb_challenge_final.kicad_pcbPaul Vincent Bezzina2026-09-151-43635/+0
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* Add files via uploadPaul Vincent Bezzina2026-09-152-0/+44286
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* Rename pcb_challenge_final.kicad_sch to main/pcb_challenge_final.kicad_schPaul Vincent Bezzina2026-09-151-0/+48411
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