diff options
| author | Paul Vincent Bezzina <109743463+Vertrex-star@users.noreply.github.com> | 2026-10-14 09:10:01 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2026-10-14 09:10:01 +0100 |
| commit | 2266a4186e7fee49e9d8111c74ed20cf04889524 (patch) | |
| tree | 1f3107797f9fa0b058760764927ace34c4a6a010 /main | |
| parent | 7f67d3cc489d78c30c57581d2506a239b845f62c (diff) | |
| download | PCB-Challenge-2026-2266a4186e7fee49e9d8111c74ed20cf04889524.zip | |
Resolved issue with 3V3 and +3.3V differences on the schematic
Diffstat (limited to 'main')
| -rw-r--r-- | main/pcb_challenge_final.kicad_pcb | 42 | ||||
| -rw-r--r-- | main/pcb_challenge_final.kicad_prl | 6 | ||||
| -rw-r--r-- | main/pcb_challenge_final.kicad_pro | 6 | ||||
| -rw-r--r-- | main/pcb_challenge_final.kicad_sch | 185 |
4 files changed, 144 insertions, 95 deletions
diff --git a/main/pcb_challenge_final.kicad_pcb b/main/pcb_challenge_final.kicad_pcb index 50be5ba..bac3080 100644 --- a/main/pcb_challenge_final.kicad_pcb +++ b/main/pcb_challenge_final.kicad_pcb @@ -34,6 +34,45 @@ (45 "User.4" user)
)
(setup
+ (stackup
+ (layer "F.SilkS"
+ (type "Top Silk Screen")
+ )
+ (layer "F.Paste"
+ (type "Top Solder Paste")
+ )
+ (layer "F.Mask"
+ (type "Top Solder Mask")
+ (thickness 0.01)
+ )
+ (layer "F.Cu"
+ (type "copper")
+ (thickness 0.035)
+ )
+ (layer "dielectric 1"
+ (type "core")
+ (thickness 1.51)
+ (material "FR4")
+ (epsilon_r 4.5)
+ (loss_tangent 0.02)
+ )
+ (layer "B.Cu"
+ (type "copper")
+ (thickness 0.035)
+ )
+ (layer "B.Mask"
+ (type "Bottom Solder Mask")
+ (thickness 0.01)
+ )
+ (layer "B.Paste"
+ (type "Bottom Solder Paste")
+ )
+ (layer "B.SilkS"
+ (type "Bottom Silk Screen")
+ )
+ (copper_finish "None")
+ (dielectric_constraints no)
+ )
(pad_to_mask_clearance 0)
(allow_soldermask_bridges_in_footprints no)
(tenting
@@ -50,6 +89,7 @@ )
(capping no)
(filling no)
+ (zone_defaults)
(pcbplotparams
(layerselection 0x00000000_00000000_55555555_5755f5ff)
(plot_on_all_layers_selection 0x00000000_00000000_00000000_00000000)
@@ -26092,7 +26132,7 @@ (at -7 -1.7)
(size 0.8 0.4)
(layers "F.Cu" "F.Mask" "F.Paste")
- (net "3v3")
+ (net "+3.3V")
(pinfunction "3V3_3")
(pintype "power_in")
(uuid "d61db001-f020-448e-b0b4-0ff5899a42cc")
diff --git a/main/pcb_challenge_final.kicad_prl b/main/pcb_challenge_final.kicad_prl index 7fa74d0..b856ad1 100644 --- a/main/pcb_challenge_final.kicad_prl +++ b/main/pcb_challenge_final.kicad_prl @@ -2,18 +2,18 @@ "board": { "active_layer": 0, "active_layer_preset": "", - "auto_track_width": true, + "auto_track_width": false, "hidden_netclasses": [], "hidden_nets": [], "high_contrast_mode": 0, "net_color_mode": 1, "opacity": { - "images": 0.6, + "images": 1.0, "pads": 1.0, "shapes": 1.0, "tracks": 1.0, "vias": 1.0, - "zones": 0.6 + "zones": 1.0 }, "prototype_zone_fills": false, "selection_filter": { diff --git a/main/pcb_challenge_final.kicad_pro b/main/pcb_challenge_final.kicad_pro index 4b18639..916c6ed 100644 --- a/main/pcb_challenge_final.kicad_pro +++ b/main/pcb_challenge_final.kicad_pro @@ -124,7 +124,7 @@ }, "rules": { "max_error": 0.005, - "min_clearance": 0.0, + "min_clearance": 0.12, "min_connection": 0.0, "min_copper_edge_clearance": 0.5, "min_groove_width": 0.0, @@ -137,7 +137,7 @@ "min_text_height": 0.8, "min_text_thickness": 0.08, "min_through_hole_diameter": 0.3, - "min_track_width": 0.2, + "min_track_width": 0.15, "min_via_annular_width": 0.1, "min_via_diameter": 0.5, "solder_mask_to_copper_clearance": 0.0, @@ -645,7 +645,7 @@ "uuid": "a2338fc7-ce61-4d61-979a-e8ad262cca17" } ], - "used_designators": "", + "used_designators": "#PWR11", "variants": [] }, "sheets": [ diff --git a/main/pcb_challenge_final.kicad_sch b/main/pcb_challenge_final.kicad_sch index 293fbe0..fd70fcf 100644 --- a/main/pcb_challenge_final.kicad_sch +++ b/main/pcb_challenge_final.kicad_sch @@ -7893,7 +7893,7 @@ )
(wire
(pts
- (xy 304.292 77.47) (xy 308.864 77.47)
+ (xy 304.292 77.47) (xy 309.88 77.47)
)
(stroke
(width 0)
@@ -8833,6 +8833,16 @@ )
(wire
(pts
+ (xy 205.74 22.86) (xy 212.852 22.86)
+ )
+ (stroke
+ (width 0)
+ (type default)
+ )
+ (uuid "52cea997-cc16-4945-827c-e541c3bfd8a5")
+ )
+ (wire
+ (pts
(xy 586.74 57.15) (xy 596.9 57.15)
)
(stroke
@@ -37888,6 +37898,84 @@ )
)
(symbol
+ (lib_id "power:VDD")
+ (at 309.88 77.47 0)
+ (unit 1)
+ (body_style 1)
+ (exclude_from_sim no)
+ (in_bom yes)
+ (on_board yes)
+ (in_pos_files yes)
+ (dnp no)
+ (uuid "3aeb3de3-e4e3-4f4e-84f8-3655f63c5521")
+ (property "Reference" "#PWR011"
+ (at 309.88 81.28 0)
+ (hide yes)
+ (show_name no)
+ (do_not_autoplace no)
+ (effects
+ (font
+ (size 1.27 1.27)
+ )
+ )
+ )
+ (property "Value" "+3.3V"
+ (at 307.594 73.914 0)
+ (show_name no)
+ (do_not_autoplace no)
+ (effects
+ (font
+ (size 1.27 1.27)
+ )
+ (justify left)
+ )
+ )
+ (property "Footprint" ""
+ (at 309.88 77.47 0)
+ (hide yes)
+ (show_name no)
+ (do_not_autoplace no)
+ (effects
+ (font
+ (size 1.27 1.27)
+ )
+ )
+ )
+ (property "Datasheet" ""
+ (at 309.88 77.47 0)
+ (hide yes)
+ (show_name no)
+ (do_not_autoplace no)
+ (effects
+ (font
+ (size 1.27 1.27)
+ )
+ )
+ )
+ (property "Description" "Power symbol creates a global label with name \"VDD\""
+ (at 309.88 77.47 0)
+ (hide yes)
+ (show_name no)
+ (do_not_autoplace no)
+ (effects
+ (font
+ (size 1.27 1.27)
+ )
+ )
+ )
+ (pin "1"
+ (uuid "5ad69c0b-2469-4f97-8116-2884876f0244")
+ )
+ (instances
+ (project "pcb_challenge_final"
+ (path "/a2338fc7-ce61-4d61-979a-e8ad262cca17"
+ (reference "#PWR011")
+ (unit 1)
+ )
+ )
+ )
+ )
+ (symbol
(lib_id "Switch:SW_Push")
(at 247.142 35.56 0)
(unit 1)
@@ -45022,7 +45110,7 @@ )
(symbol
(lib_id "power:VDD")
- (at 212.852 22.86 90)
+ (at 205.74 22.86 0)
(unit 1)
(body_style 1)
(exclude_from_sim no)
@@ -45030,10 +45118,9 @@ (on_board yes)
(in_pos_files yes)
(dnp no)
- (fields_autoplaced yes)
(uuid "87c6779e-465a-4ea1-a76e-2ca6697c1aa9")
(property "Reference" "#PWR010"
- (at 216.662 22.86 0)
+ (at 205.74 26.67 0)
(hide yes)
(show_name no)
(do_not_autoplace no)
@@ -45043,18 +45130,19 @@ )
)
)
- (property "Value" "3v3"
- (at 207.518 22.86 0)
+ (property "Value" "+3.3V"
+ (at 203.454 19.304 0)
(show_name no)
(do_not_autoplace no)
(effects
(font
(size 1.27 1.27)
)
+ (justify left)
)
)
(property "Footprint" ""
- (at 212.852 22.86 0)
+ (at 205.74 22.86 0)
(hide yes)
(show_name no)
(do_not_autoplace no)
@@ -45065,7 +45153,7 @@ )
)
(property "Datasheet" ""
- (at 212.852 22.86 0)
+ (at 205.74 22.86 0)
(hide yes)
(show_name no)
(do_not_autoplace no)
@@ -45076,7 +45164,7 @@ )
)
(property "Description" "Power symbol creates a global label with name \"VDD\""
- (at 212.852 22.86 0)
+ (at 205.74 22.86 0)
(hide yes)
(show_name no)
(do_not_autoplace no)
@@ -55634,85 +55722,6 @@ )
)
(symbol
- (lib_id "power:VDD")
- (at 308.864 77.47 270)
- (unit 1)
- (body_style 1)
- (exclude_from_sim no)
- (in_bom yes)
- (on_board yes)
- (in_pos_files yes)
- (dnp no)
- (fields_autoplaced yes)
- (uuid "df8aef48-eb05-47bf-8382-fe887bb7659d")
- (property "Reference" "#PWR03"
- (at 305.054 77.47 0)
- (hide yes)
- (show_name no)
- (do_not_autoplace no)
- (effects
- (font
- (size 1.27 1.27)
- )
- )
- )
- (property "Value" "3v3"
- (at 312.42 77.4699 90)
- (show_name no)
- (do_not_autoplace no)
- (effects
- (font
- (size 1.27 1.27)
- )
- (justify left)
- )
- )
- (property "Footprint" ""
- (at 308.864 77.47 0)
- (hide yes)
- (show_name no)
- (do_not_autoplace no)
- (effects
- (font
- (size 1.27 1.27)
- )
- )
- )
- (property "Datasheet" ""
- (at 308.864 77.47 0)
- (hide yes)
- (show_name no)
- (do_not_autoplace no)
- (effects
- (font
- (size 1.27 1.27)
- )
- )
- )
- (property "Description" "Power symbol creates a global label with name \"VDD\""
- (at 308.864 77.47 0)
- (hide yes)
- (show_name no)
- (do_not_autoplace no)
- (effects
- (font
- (size 1.27 1.27)
- )
- )
- )
- (pin "1"
- (uuid "6792fb0a-8986-49da-8592-af389afe6c9e")
- )
- (instances
- (project "pcb_challenge_final"
- (path "/a2338fc7-ce61-4d61-979a-e8ad262cca17"
- (reference "#PWR03")
- (unit 1)
- )
- )
- )
- )
- (symbol
(lib_id "power:GND")
(at 269.24 455.93 0)
(unit 1)
|
