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| author | Paul Vincent Bezzina <109743463+Vertrex-star@users.noreply.github.com> | 2026-10-14 08:02:23 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2026-10-14 08:02:23 +0100 |
| commit | ea6e83550b752ad4eb964577b5110b4e1ad3631b (patch) | |
| tree | 570511c8e7270479c7bef5d3a98aaf0ce0431220 /README.md | |
| parent | bf53df0ddf9fc1da967a21721228f83fd883f7a1 (diff) | |
| download | PCB-Challenge-2026-ea6e83550b752ad4eb964577b5110b4e1ad3631b.zip | |
Update README.md
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -54,7 +54,7 @@ The keep out zone of the ESP32 antenna does not have to cover any PCB area, it c ### Trace & Clearance Rules - Minimum trace width: 0.15 mm (6 mil). -- Minimum clearance (trace to trace, trace to pad, trace to via): 0.15 mm (6 mil). +- Minimum clearance (trace to trace, trace to pad, trace to via): 0.12 mm (6 mil) (changed from 0.15mm to 0.12mm due to the pads of the flip flop being seperated by 0.12mm). - Minimum copper to board edge clearance: 0.3 mm. - These values should be set as the global minimum in KiCad's Clearance rules so DRC enforces them automatically. We will check the DRC ourselves when judging. |