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authorPaul Vincent Bezzina <109743463+Vertrex-star@users.noreply.github.com>2026-10-14 12:38:44 +0100
committerGitHub <noreply@github.com>2026-10-14 12:38:44 +0100
commitcfaee50808ef292fb3a283722a44f8d58ab12638 (patch)
treec013e5cd256d35dc0ffccbe6d0056b94dbb2f28d /main/issues_resolved.md
parent3419f27e4f17e3a66e98bb94624cd6ec21e403ff (diff)
downloadPCB-Challenge-2026-cfaee50808ef292fb3a283722a44f8d58ab12638.zip
Resolved issues
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+C1-C8, R1, SW1 and SW3 did not have a footprint. The transistor did not have the correct nets due to being numbered 1, 5 and 6 rather than 1, 2 and 3.
+3v3 instead of +3.3V power net.
+Input 1, Input2, Input 3 and Input 4 rather than b1, b2, b3 and 4.