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| author | Paul Vincent Bezzina <109743463+Vertrex-star@users.noreply.github.com> | 2026-10-14 12:31:13 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2026-10-14 12:31:13 +0100 |
| commit | 3790d3b588130668b2d9832a9fe209a65a471ea7 (patch) | |
| tree | 23ef6787bbcf247ef633e53dcf09106f2acd1af8 /main/pcb_challenge_final.kicad_pro | |
| parent | 1797f7517a7d64011df9625c5f8132d43fc49c4b (diff) | |
| download | PCB-Challenge-2026-3790d3b588130668b2d9832a9fe209a65a471ea7.zip | |
Fixed reported schematic and PCB issues
C1-C8, R1 and SW1 and SW3 were not assigned a footprint. Few mistakes with the net labels now resolved Transistors actually have nets.
Diffstat (limited to 'main/pcb_challenge_final.kicad_pro')
| -rw-r--r-- | main/pcb_challenge_final.kicad_pro | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/main/pcb_challenge_final.kicad_pro b/main/pcb_challenge_final.kicad_pro index 916c6ed..a4b1521 100644 --- a/main/pcb_challenge_final.kicad_pro +++ b/main/pcb_challenge_final.kicad_pro @@ -645,7 +645,7 @@ "uuid": "a2338fc7-ce61-4d61-979a-e8ad262cca17" } ], - "used_designators": "#PWR11", + "used_designators": "Q16-29", "variants": [] }, "sheets": [ |