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authorPaul Vincent Bezzina <109743463+Vertrex-star@users.noreply.github.com>2026-10-14 12:53:39 +0100
committerGitHub <noreply@github.com>2026-10-14 12:53:39 +0100
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+## Issues
+1. C1-C8, R1, SW1 and SW3 did not have a footprint.
+2. The transistor did not have the correct nets due to being numbered 1, 5 and 6 rather than 1, 2 and 3.
+3. 3v3 instead of +3.3V power net.
+4. Input 1, Input2, Input 3 and Input 4 rather than b1, b2, b3 and 4.
+
+#### Credits to:
+Mickey Techachokwiwat and Lutfi Cengiz for finding these issues and reporting them to me.