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| author | Paul Vincent Bezzina <109743463+Vertrex-star@users.noreply.github.com> | 2026-10-13 12:07:59 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2026-10-13 12:07:59 +0100 |
| commit | bf53df0ddf9fc1da967a21721228f83fd883f7a1 (patch) | |
| tree | 3d0ae5d3ab2df106bd70a91a2a7f7d0336758a6d /warmup/answer.md | |
| parent | 31b9dc061ce705ae033e36f30113eb419dc3e794 (diff) | |
| download | PCB-Challenge-2026-bf53df0ddf9fc1da967a21721228f83fd883f7a1.zip | |
Update answer.md
Diffstat (limited to 'warmup/answer.md')
| -rw-r--r-- | warmup/answer.md | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/warmup/answer.md b/warmup/answer.md index 4a9f4c5..6768595 100644 --- a/warmup/answer.md +++ b/warmup/answer.md @@ -2,7 +2,7 @@ ## Project Description -This board is a **serial input 8 bit adder with a fixed value match detector**. Two single bit data streams (Input 1 and Input 2) are clocked into two separate 8-bit serial in/parallel out shift registers. Once eight bits have been loaded, the two bytes are added by a cascaded 8 bit binary adder. The sum goes to a hard-wired equality comparator, which raises the output **F** only when the sum equals a predetermined constant. +This board is a **serial input 8 bit adder with a fixed value match detector**. Two single bit data streams (Input 1 and Input 2) are clocked into two separate 8 bit serial in/parallel out shift registers. Once eight bits have been loaded, the two bytes are added by a cascaded 8 bit binary adder. The sum goes to a hard-wired equality comparator, which raises the output **F** only when the sum equals a predetermined constant. ## Functional Blocks |
